EP610PC-25 vs EP910PC-35 Comparaison
Comparaison détaillée côte à côte de EP610PC-25 par Altera et EP910PC-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610PC-25 | EP910PC-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $8,70 |
| Device Family | Classic EPLD (EP610 series) | — |
| Macro Cells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Technology | CMOS, EPROM (UV-erasable) | CMOS, UV-erasable/OTP |
| Device Type | OT PLD, PAL-type, CMOS | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | 4 | 12 |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | 24 |
| Boîtier | PDIP-24 (0.3 inch, through-hole) | 40-pin PDIP (Plastic DIP) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Type de montage | Through-Hole (DIP) | Through-Hole |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Family | — | Classic EPLD |
| Macrocells | — | 24 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Tension d'alimentation | — | 5 V |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |