EP610PC-25 vs EP910PC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610PC-25 disebabkan oleh Altera dan EP910PC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610PC-25 EP910PC-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family Classic EPLD (EP610 series) —
Macro Cells 16 —
Usable Gates 300 —
Propagation Delay (tpd) 25 ns —
Maximum Pipelined Data Rate 100 MHz —
Supply Voltage (Vcc) 5 V (nominal) —
Technology CMOS, EPROM (UV-erasable) CMOS, UV-erasable/OTP
Device Type OT PLD, PAL-type, CMOS EPLD (Erasable Programmable Logic Device)
Dedicated Inputs 4 12
I/O Pins 20 (bidirectional, JTAG-programmable OE per macrocell) 24
Kemasan PDIP-24 (0.3 inch, through-hole) 40-pin PDIP (Plastic DIP)
Suhu Operasi [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
Programming Method EPROM (UV-erasable), via Altera programming hardware UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools
Jenis Pemasangan Through-Hole (DIP) Through-Hole
Status RoHS [DATA_NEEDED: RoHS status] —
Family — Classic EPLD
Macrocells — 24
Total Inputs — 36
Product Terms — 240
Propagation Delay (tPD) — 35 ns
Maximum Counter Frequency — 37 MHz
Internal Performance Frequency — 100 MHz
Tegangan Pemberi Arus — 5 V
Architecture — PAL-type sum-of-products, AND/OR array
Compliance / RoHS — [DATA_NEEDED: RoHS status - legacy part]

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