EP910DC-15 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910DC-15 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-15 | EP910DC-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 12 | 24 |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 40 ns |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Operating Temperature | 0C to +70C (commercial) | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Package | 24-pin ceramic DIP (DC) | DIP-40 (ceramic, through-hole) |
| Mounting Type | Through-Hole | Through-Hole |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: not explicitly stated in verified data] | [DATA_NEEDED: rohs_status] |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Supply Voltage | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |