EP910DC-15 vs EP910DC-40 Comparaison
Comparaison détaillée côte à côte de EP910DC-15 par Altera et EP910DC-40 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910DC-15 | EP910DC-40 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,75 | $13,95 |
| Family | Altera Classic EPLD | — |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 12 | 24 |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 40 ns |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Température de fonctionnement | 0C to +70C (commercial) | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Boîtier | 24-pin ceramic DIP (DC) | DIP-40 (ceramic, through-hole) |
| Type de montage | Through-Hole | Through-Hole |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: not explicitly stated in verified data] | [DATA_NEEDED: rohs_status] |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Tension d'alimentation | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |