EP910DC-30 vs EP9100C-30 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP9100C-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP910DC-30
EP910DC-30 - 900-Gate UV EPLD, 24 Macrocells, DIP-40 | Altera / Intel
EP910DC-30 ObsoleteAltera
EP9100C-30
EP9100C-30 - 900 Gates Classic EPLD, 30ns CMOS | Intel / Altera
EP9100C-30 ObsoleteSpecification Comparison
| Parameter | EP910DC-30 | EP9100C-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $7.95 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | β |
| Gate Count | 900 usable gates | β |
| Macrocells | 24 | 48 |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns |
| Clock Frequency (fCNT) | 33.3 MHz | β |
| Dedicated Inputs | 36 | 24 |
| Outputs (Macrocells) | 24 | β |
| External Clock Pins | 2 (CLK1, CLK2) | β |
| Supply Voltage | 5 V | β |
| Process Technology | CMOS | β |
| Programming Method | UV-Erasable / OTP | JEDEC via Altera APU or compatible programmer |
| Package | DIP-40 (through-hole, 600 mil) | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Mounting Type | Through-Hole | Through-Hole (DIP) / Surface Mount (PLCC) |
| Logic Density | β | 900 usable gates (approx.) |
| Flip-Flops | β | 24 |
| Maximum Toggle Frequency (fMAX) | β | 62.5 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| I/O Standard | β | TTL-compatible |
| Technology | β | CMOS, UV-erasable (window) or OTP |
| RoHS Status | β | [DATA_NEEDED: rohs_status] |
| Military Grade Variant | β | EP9100C-30/883 (MIL-STD-883 compliant) |