EP910DC-30 vs EP9100C-30 比較
詳細並排比較 EP910DC-30 由 Intel 與 EP9100C-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DC-30 | EP9100C-30 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | — |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 48 |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 24 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| 供應電壓 | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | JEDEC via Altera APU or compatible programmer |
| 封裝 | DIP-40 (through-hole, 600 mil) | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 安裝類型 | Through-Hole | Through-Hole (DIP) / Surface Mount (PLCC) |
| Logic Density | — | 900 usable gates (approx.) |
| Flip-Flops | — | 24 |
| Maximum Toggle Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| I/O Standard | — | TTL-compatible |
| Technology | — | CMOS, UV-erasable (window) or OTP |
| RoHS 狀態 | — | [DATA_NEEDED: rohs_status] |
| Military Grade Variant | — | EP9100C-30/883 (MIL-STD-883 compliant) |