EP910DC-35 vs EP910ILC-12 Comparison
Detailed side-by-side comparison of EP910DC-35 by Altera and EP910ILC-12 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910DC-35
EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
EP910DC-35 ObsoleteSpecification Comparison
| Parameter | EP910DC-35 | EP910ILC-12 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.95 | $12.40 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | β |
| Family | Classic EPLD EP910 | Altera EP910 Classic EPLD |
| Architecture | PAL-type sum-of-products AND-OR array | β |
| Usable Gates | 900 gates | 450 (typical) |
| Macrocells | 24 | β |
| Product Terms | 240 | β |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 | β |
| Total Inputs | 36 | β |
| Propagation Delay (tpd) | 35 ns | β |
| Maximum Clock Frequency | 37 MHz (typical, internal) | β |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | -40 Β°C to +85 Β°C (industrial grade, 'I' suffix) |
| Package | 40-pin CDIP (Ceramic DIP) with quartz window | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Lead Pitch | 2.540 mm | β |
| Termination Style | Through-Hole | β |
| Programming Method | JEDEC fuse map via device programmer; UV erase | Altera programming algorithm (serial/parallel master-slave) |
| Technology | CMOS, UV-erasable EPROM cell | β |
| RoHS Status | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | β | 24 |
| Propagation Delay (tPD) | β | 12 ns (max) |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Nominal Supply | β | 5 V |
| Memory Technology | β | UV-erasable CMOS EPROM |
| Mounting Type | β | Surface Mount |
| Configuration Storage | β | Non-volatile EPROM (instant-on) |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Number of Pins | β | 28 |
| Feedback Paths | β | 16 dedicated |