EP910DC-35 vs EP910ILC-12 对比
详细并排对比 EP910DC-35 出自 Altera 和 EP910ILC-12 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DC-35 | EP910ILC-12 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.95 | $12.40 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | Altera EP910 Classic EPLD |
| Architecture | PAL-type sum-of-products AND-OR array | — |
| Usable Gates | 900 gates | 450 (typical) |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| 最大时钟频率 | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作温度 | 0 °C to +70 °C (commercial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| 封装 | 40-pin CDIP (Ceramic DIP) with quartz window | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | Altera programming algorithm (serial/parallel master-slave) |
| Technology | CMOS, UV-erasable EPROM cell | — |
| RoHS 状态 | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| 安装类型 | — | Surface Mount |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |
| 引脚数 | — | 28 |
| Feedback Paths | — | 16 dedicated |