EP910DM-40 vs EP910JM-40 Comparison
Detailed side-by-side comparison of EP910DM-40 by Altera and EP910JM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DM-40 | EP910JM-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | — |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 12 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| External Clocks | 2 | — |
| Process Technology | CMOS | CMOS |
| Package | 40-pin Ceramic DIP (Cerdip) with UV window | JLCC-28 (windowed ceramic, J-lead) |
| Mounting Type | Through-Hole (DIP) | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] |
| Supply Voltage | 5 V | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Device Family | — | Altera Classic EPLD |
| Series | — | EP910 |
| Logic Type | — | EPLD (UV-Erasable PAL-type) |
| I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| External Clock Inputs | — | 2 |
| Programming Method | — | UV erase + EPROM programmer |