EP910ILC-12 vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910ILC-12 EP910DC-35
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera EP910 Classic EPLD Classic EPLD EP910
Number of Macrocells 24 —
Usable Gates 450 (typical) 900 gates
Propagation Delay (tPD) 12 ns (max) —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Nominal Supply 5 V —
Memory Technology UV-erasable CMOS EPROM —
Package 28-PLCC (J-Lead, 11.5 x 11.5 mm) 40-pin CDIP (Ceramic DIP) with quartz window
Mounting Type Surface Mount —
Operating Temperature -40 °C to +85 °C (industrial grade, 'I' suffix) 0 °C to +70 °C (commercial)
Configuration Storage Non-volatile EPROM (instant-on) —
Programming Method Altera programming algorithm (serial/parallel master-slave) JEDEC fuse map via device programmer; UV erase
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status [DATA_NEEDED: RoHS status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Number of Pins 28 —
Feedback Paths 16 dedicated —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Macrocells — 24
Product Terms — 240
Dedicated Inputs — 12
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maximum Clock Frequency — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

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