EP910ILC-12 vs EP910IDI-15 Comparison

Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910ILC-12 EP910IDI-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera EP910 Classic EPLD Classic EPLD
Number of Macrocells 24 —
Usable Gates 450 (typical) —
Propagation Delay (tPD) 12 ns (max) —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Nominal Supply 5 V —
Memory Technology UV-erasable CMOS EPROM —
Package 28-PLCC (J-Lead, 11.5 x 11.5 mm) 40-pin CDIP (CerDIP) with quartz window
Mounting Type Surface Mount Through-hole (DIP)
Operating Temperature -40 °C to +85 °C (industrial grade, 'I' suffix) -40C to +85C (industrial, "I" grade)
Configuration Storage Non-volatile EPROM (instant-on) —
Programming Method Altera programming algorithm (serial/parallel master-slave) —
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Number of Pins 28 —
Feedback Paths 16 dedicated —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 450 gates
Macrocells — 24
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Supply Voltage (Vcc) — 5 V
Technology — CMOS EPROM
Program/Erase Method — UV-erasable windowed CerDIP
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

Datasheets & Resources

Browse All Products Create BOM Request Quote