EP910ILC-12 vs EP910IDI-15 Comparación
Comparación detallada lado a lado de EP910ILC-12 por Intel y EP910IDI-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910ILC-12 | EP910IDI-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $12,40 | $29,00 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | — |
| Propagation Delay (tPD) | 12 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| Encapsulado | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 40-pin CDIP (CerDIP) with quartz window |
| Tipo de montaje | Surface Mount | Through-hole (DIP) |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial grade, 'I' suffix) | -40C to +85C (industrial, "I" grade) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Número de pines | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 gates |
| Macrocells | — | 24 |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EPROM |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |