EP910ILC-15N vs EP610ILC-10 Comparison
Detailed side-by-side comparison of EP910ILC-15N by Altera and EP610ILC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Specification Comparison
| Parameter | EP910ILC-15N | EP610ILC-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic | — |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-Erasable / OTP PLD |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Pins | 36 | — |
| Dedicated Input Pins | 16 | — |
| Package | PLCC-44 (J-lead, surface mount) | PLCC-28 (plastic J-lead chip carrier) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or solder) |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| I/O Pins | — | 16 |
| Dedicated Inputs | — | 4 |
| Supply Voltage | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |