EP910ILC-50 vs EP910ILC-12 Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910ILC-12 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-50 | EP910ILC-12 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera EP910 Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | 450 (typical) |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| Package | PLCC-44 (J-lead) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Mounting Type | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | — |
| Operating Temperature | 0C to +70C (commercial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Number of Pins | — | 28 |
| Feedback Paths | — | 16 dedicated |