EP910ILC-50 vs EP910ILC-12 比較
詳細な並列比較: EP910ILC-50 メーカー: Intel および EP910ILC-12 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910ILC-50 | EP910ILC-12 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.85 | $12.40 |
| Family | Altera Classic EPLD | Altera EP910 Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | 450 (typical) |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| パッケージ | PLCC-44 (J-lead) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| 実装タイプ | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | — |
| 動作温度 | 0C to +70C (commercial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| MSLレベル | — | [DATA_NEEDED: MSL level] |
| ピン数 | — | 28 |
| Feedback Paths | — | 16 dedicated |