EP910ILC-50 vs EP910ILI-25 Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910ILI-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-50 | EP910ILI-25 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| Package | PLCC-44 (J-lead) | PLCC-44 (windowed ceramic, J-lead) |
| Mounting Type | Surface Mount (socket-compatible) | — |
| Technology | CMOS EPROM, UV-erasable | CMOS, EPROM |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Non-compliant (windowed ceramic package) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | EP910 (Classic EPLD) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 (maximum) |
| Propagation Delay (tPD) | — | 25 ns |
| Architecture | — | PAL-type with global interconnect bus |
| Operating Voltage | — | 5 V (4.75 V to 5.25 V) |
| Programming Method | — | UV-erasable (windowed), MAX+PLUS II programmer |
| Logic Test Circuitry | — | On-board JTAG-compatible test |