EP910ILC-50 vs EP910ILI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-50 sa pamamagitan ng Intel at EP910ILI-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-50 | EP910ILI-25 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| Packhaging | PLCC-44 (J-lead) | PLCC-44 (windowed ceramic, J-lead) |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | — |
| Technology | CMOS EPROM, UV-erasable | CMOS, EPROM |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (windowed ceramic package) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | EP910 (Classic EPLD) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 (maximum) |
| Propagation Delay (tPD) | — | 25 ns |
| Architecture | — | PAL-type with global interconnect bus |
| Operating Voltage | — | 5 V (4.75 V to 5.25 V) |
| Programming Method | — | UV-erasable (windowed), MAX+PLUS II programmer |
| Logic Test Circuitry | — | On-board JTAG-compatible test |