EP910IPC-12 vs EP910IPC-50 Comparison
Detailed side-by-side comparison of EP910IPC-12 by Altera and EP910IPC-50 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-12 | EP910IPC-50 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.20 | $13.85 |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | β |
| Usable Gates | 450 | β |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 10 | β |
| I/O Pins | 24 | β |
| Package | 40-pin PDIP | 40-pin Ceramic DIP (IPC, windowed) |
| Mounting Type | Through Hole | Through-Hole (DIP) |
| Technology | CMOS EPLD (UV-erasable or OTP) | CMOS EPROM cell |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Programming Toolchain | MAX+PLUS II | β |
| Logic Capacity | Equivalent to ~24 PAL16V8s | [DATA_NEEDED: macrocell count / equivalent gates] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | β | Erasable Programmable Logic Device (EPLD) |
| Propagation Delay (tPD) | β | 50 ns |
| Clock-to-Output (tCO) | β | 35 ns |
| Maximum Toggle Frequency | β | [DATA_NEEDED: fMAX] |
| User I/O Pins | β | 24 |
| Programming Method | β | Off-board EPROM programmer + UV erase |
| Erasure Method | β | UV light through ceramic window (IPC package) |