EP910IPC-12 vs EP910IPC-50 비교
다음의 상세 나란히 비교: EP910IPC-12 제조: Altera 및 EP910IPC-50 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910IPC-12 | EP910IPC-50 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $14.20 | $13.85 |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| 패키지 | 40-pin PDIP | 40-pin Ceramic DIP (IPC, windowed) |
| 실장 유형 | Through Hole | Through-Hole (DIP) |
| Technology | CMOS EPLD (UV-erasable or OTP) | CMOS EPROM cell |
| 동작 온도 | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | [DATA_NEEDED: macrocell count / equivalent gates] |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Propagation Delay (tPD) | — | 50 ns |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |