EP910IPC-12 vs EP910IPC-50 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910IPC-12 disebabkan oleh Altera dan EP910IPC-50 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910IPC-12 | EP910IPC-50 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| Kemasan | 40-pin PDIP | 40-pin Ceramic DIP (IPC, windowed) |
| Jenis Pemasangan | Through Hole | Through-Hole (DIP) |
| Technology | CMOS EPLD (UV-erasable or OTP) | CMOS EPROM cell |
| Suhu Operasi | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | [DATA_NEEDED: macrocell count / equivalent gates] |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Propagation Delay (tPD) | — | 50 ns |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |