EP910IPC-50 vs EP910IPC-12 Comparison
Detailed side-by-side comparison of EP910IPC-50 by Altera and EP910IPC-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-50 | EP910IPC-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.85 | $14.20 |
| Product Type | Erasable Programmable Logic Device (EPLD) | β |
| Family | Altera Classic EPLD | Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | Equivalent to ~24 PAL16V8s |
| Propagation Delay (tPD) | 50 ns | β |
| Clock-to-Output (tCO) | 35 ns | β |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | β |
| User I/O Pins | 24 | β |
| Package | 40-pin Ceramic DIP (IPC, windowed) | 40-pin PDIP |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS EPROM cell | CMOS EPLD (UV-erasable or OTP) |
| Programming Method | Off-board EPROM programmer + UV erase | β |
| Erasure Method | UV light through ceramic window (IPC package) | β |
| Mounting Type | Through-Hole (DIP) | Through Hole |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS status] |
| Macrocells | β | 24 |
| Usable Gates | β | 450 |
| Maximum Operating Frequency (fMAX) | β | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | β | 12 ns |
| Dedicated Inputs | β | 10 |
| I/O Pins | β | 24 |
| Programming Toolchain | β | MAX+PLUS II |