EP910IPC-50 vs EP910IPC-12 Vergleich
Detaillierter Direktvergleich von EP910IPC-50 von Altera und EP910IPC-12 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910IPC-50 | EP910IPC-12 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $13,85 | $14,20 |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | Equivalent to ~24 PAL16V8s |
| Propagation Delay (tPD) | 50 ns | — |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | — |
| Gehäuse | 40-pin Ceramic DIP (IPC, windowed) | 40-pin PDIP |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS EPROM cell | CMOS EPLD (UV-erasable or OTP) |
| Programming Method | Off-board EPROM programmer + UV erase | — |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Montageart | Through-Hole (DIP) | Through Hole |
| RoHS-Status | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS status] |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 24 |
| Programming Toolchain | — | MAX+PLUS II |