EP910IPC-50 vs EP910IPC-15 Comparison
Detailed side-by-side comparison of EP910IPC-50 by Altera and EP910IPC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-50 | EP910IPC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.85 | $7.95 |
| Product Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | β |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | β |
| Propagation Delay (tPD) | 50 ns | 15 ns |
| Clock-to-Output (tCO) | 35 ns | β |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | β |
| User I/O Pins | 24 | β |
| Package | 40-pin Ceramic DIP (IPC, windowed) | PDIP-40 (Plastic DIP, 40-pin) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial, IPC suffix) |
| Technology | CMOS EPROM cell | β |
| Programming Method | Off-board EPROM programmer + UV erase | JEDEC fuse map via Altera EPLD programmer |
| Erasure Method | UV light through ceramic window (IPC package) | β |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | β | Altera Classic EPLD (EP910 series) |
| Architecture | β | PAL-type, CMOS |
| Macrocells | β | 24 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Product Terms | β | 240 |
| External Clocks | β | 2 |
| Process Technology | β | CMOS |
| Pin Count | β | 40 |