EP910IPC-50 vs EP910IPC-15 तुलना
विस्तृत दोनों ओर की तुलना EP910IPC-50 द्वारा Altera और EP910IPC-15 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910IPC-50 | EP910IPC-15 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Product Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | — |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | 15 ns |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | — |
| पैकेज | 40-pin Ceramic DIP (IPC, windowed) | PDIP-40 (Plastic DIP, 40-pin) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| ऑपरेटिंग तापमान | -40C to +85C (industrial) | 0C to +70C (commercial, IPC suffix) |
| Technology | CMOS EPROM cell | — |
| Programming Method | Off-board EPROM programmer + UV erase | JEDEC fuse map via Altera EPLD programmer |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| माउंटिंग प्रकार | Through-Hole (DIP) | Through-Hole |
| RoHS स्थिति | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Architecture | — | PAL-type, CMOS |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| पिन काउंट | — | 40 |