EP910JC-30 vs EP910JC-35 Comparison
Detailed side-by-side comparison of EP910JC-30 by Intel and EP910JC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-30 | EP910JC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $9.95 |
| Family | Classic EPLD (MAX-style) | β |
| Propagation Delay (tpd) | 30 ns | β |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | 36 |
| Product Terms | 240 | β |
| Outputs | 10 dedicated | β |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM, UV-erasable / OTP |
| Package | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to 70C (Commercial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | β |
| Mounting Type | Surface Mount (socket-mountable) | Surface Mount (PLCC socket recommended) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs status] |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | β |
| Logic Family | β | Classic EPLD (CMOS EPROM) |
| I/O Pins | β | 24 |
| Propagation Delay (max) | β | 38 ns (tPD) |
| Maximum Clock Frequency | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Package Type | β | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | β | J BEND |
| Package Code | β | QCCJ |
| Package Shape | β | SQUARE |
| Temperature Grading | β | COMMERCIAL |
| Equivalent Gates | β | Approx. 900 usable gates |