EP910JC-30 vs EP910JC-35 对比
详细并排对比 EP910JC-30 出自 Intel 和 EP910JC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910JC-30 | EP910JC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $9.95 |
| Family | Classic EPLD (MAX-style) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | 36 |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM, UV-erasable / OTP |
| 封装 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0C to 70C (Commercial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| 安装类型 | Surface Mount (socket-mountable) | Surface Mount (PLCC socket recommended) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs status] |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Logic Family | — | Classic EPLD (CMOS EPROM) |
| I/O Pins | — | 24 |
| Propagation Delay (max) | — | 38 ns (tPD) |
| 最大时钟频率 | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | — | J BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Temperature Grading | — | COMMERCIAL |
| Equivalent Gates | — | Approx. 900 usable gates |