EP910JC-30 vs EP910LC-30Y Comparison
Detailed side-by-side comparison of EP910JC-30 by Intel and EP910LC-30Y by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-30 | EP910LC-30Y |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $25.40 |
| Family | Classic EPLD (MAX-style) | Altera Classic EPLD |
| Propagation Delay (tpd) | 30 ns | β |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| Product Terms | 240 | β |
| Outputs | 10 dedicated | β |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EPROM, UV-erasable | β |
| Package | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PLCC-44 |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | Commercial 0C to +70C |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | β |
| Mounting Type | Surface Mount (socket-mountable) | Surface Mount (PLCC socket) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | β |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | β | 450 |
| Pin-to-Pin Delay (tPD) | β | 30 ns |
| Counter Frequency (fMAX) | β | 100 MHz (family maximum) |
| Supply Voltage | β | 5 V (TTL-compatible) |
| Process Technology | β | CMOS, UV-erasable / OTP |
| Speed/Power Grade | β | LC (low-power, 30ns) |
| Processing Flow | β | Y (extended reliability) |
| Logic Compatibility | β | 100% TTL emulation |