EP910JC-35 vs EP910JC-30 Comparison
Detailed side-by-side comparison of EP910JC-35 by Altera and EP910JC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-35 | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.75 |
| Logic Family | Classic EPLD (CMOS EPROM) | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | 36 |
| I/O Pins | 24 | β |
| Propagation Delay (max) | 38 ns (tPD) | β |
| Maximum Clock Frequency | 28.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to 70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | β |
| Mounting Type | Surface Mount (PLCC socket recommended) | Surface Mount (socket-mountable) |
| Terminal Form | J BEND | β |
| Package Code | QCCJ | β |
| Package Shape | SQUARE | β |
| Technology | CMOS EPROM, UV-erasable / OTP | CMOS EPROM, UV-erasable |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Temperature Grading | COMMERCIAL | β |
| Equivalent Gates | Approx. 900 usable gates | β |
| Family | β | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | β | 30 ns |
| Maximum Internal Frequency (Fmax) | β | 33.3 MHz |
| Product Terms | β | 240 |
| Outputs | β | 10 dedicated |
| Supply Voltage (Vcc) | β | 5 V |
| Package | β | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Supply Current (Icc) | β | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | β | 24 macrocells (AND/OR array architecture) |