EP910JC-35 vs EP910JC-30 比較
詳細並排比較 EP910JC-35 由 Altera 與 EP910JC-30 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910JC-35 | EP910JC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | 36 |
| I/O Pins | 24 | — |
| Propagation Delay (max) | 38 ns (tPD) | — |
| 最大時脈頻率 | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | 0C to 70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| 安裝類型 | Surface Mount (PLCC socket recommended) | Surface Mount (socket-mountable) |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | CMOS EPROM, UV-erasable |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Family | — | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| 封裝 | — | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |