EP910JC-35 vs EP910JC-30 比較
詳細な並列比較: EP910JC-35 メーカー: Altera および EP910JC-30 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910JC-35 | EP910JC-30 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $9.75 |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | 36 |
| I/O Pins | 24 | — |
| Propagation Delay (max) | 38 ns (tPD) | — |
| 最大クロック周波数 | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 動作温度 | 0C to 70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| 実装タイプ | Surface Mount (PLCC socket recommended) | Surface Mount (socket-mountable) |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | CMOS EPROM, UV-erasable |
| RoHS ステータス | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Family | — | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| パッケージ | — | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |