EP910JM-40 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910JM-40 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JM-40 | EP910DC-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $13.95 |
| Device Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Series | EP910 | β |
| Logic Type | EPLD (UV-Erasable PAL-type) | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Lines | 24 | β |
| Total Inputs (max) | 36 | β |
| Total Outputs (max) | 24 | β |
| Product Terms | 240 | 240 maximum |
| External Clock Inputs | 2 | β |
| Propagation Delay (tPD) | 40 ns | β |
| Process Technology | CMOS | β |
| Package | JLCC-28 (windowed ceramic, J-lead) | DIP-40 (ceramic, through-hole) |
| Mounting Type | Surface Mount | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | [DATA_NEEDED: rohs_status] |
| Programming Method | UV erase + EPROM programmer | UV-erase + EPROM programmer; on-board logic test circuitry |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | β |
| Architecture | β | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Supply Voltage | β | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |