EP910JM-40 vs EP910DC-40 Comparaison
Comparaison détaillée côte à côte de EP910JM-40 par Altera et EP910DC-40 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910JM-40 | EP910DC-40 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $13,95 |
| Device Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Series | EP910 | — |
| Logic Type | EPLD (UV-Erasable PAL-type) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Product Terms | 240 | 240 maximum |
| External Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS | — |
| Boîtier | JLCC-28 (windowed ceramic, J-lead) | DIP-40 (ceramic, through-hole) |
| Type de montage | Surface Mount | Through-Hole |
| Statut RoHS | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | [DATA_NEEDED: rohs_status] |
| Programming Method | UV erase + EPROM programmer | UV-erase + EPROM programmer; on-board logic test circuitry |
| Température de fonctionnement | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | — |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Tension d'alimentation | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |