EP910JM-40 vs EP910DC-40 比較
詳細並排比較 EP910JM-40 由 Altera 與 EP910DC-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910JM-40 | EP910DC-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Series | EP910 | — |
| Logic Type | EPLD (UV-Erasable PAL-type) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Product Terms | 240 | 240 maximum |
| External Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS | — |
| 封裝 | JLCC-28 (windowed ceramic, J-lead) | DIP-40 (ceramic, through-hole) |
| 安裝類型 | Surface Mount | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | [DATA_NEEDED: rohs_status] |
| Programming Method | UV erase + EPROM programmer | UV-erase + EPROM programmer; on-board logic test circuitry |
| 工作溫度 | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | — |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| 供應電壓 | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |