EP910LC-25 vs EP910LC-32 Comparison

Detailed side-by-side comparison of EP910LC-25 by Intel and EP910LC-32 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LC-25 EP910LC-32
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family Altera Classic EPLD —
Macrocells 24 —
Logic Gates [DATA_NEEDED: logic gate count] —
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 16 —
Package 28-pin PLCC (LC suffix) PLCC-32
Mounting Type Surface Mount Surface Mount (PLCC socket or direct solder)
Technology CMOS (EPROM-based) —
Operating Voltage [DATA_NEEDED: VCC range] —
Operating Temperature 0C to +70C (commercial) —
Programmable Yes (EPROM, UV-erasable on windowed variants) —
I/O Pins [DATA_NEEDED: I/O count] —
RoHS Status [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Maximum Frequency [DATA_NEEDED: fMAX] —
Device Family — Altera Classic EPLD
Number of Macrocells — 24
Number of Usable Gates — 900 gates (typical)
Number of Dedicated Inputs — 10
Number of I/O Pins — 20
Speed Grade — -32
Maximum Toggle Frequency (fMAX) — [DATA_NEEDED: fMAX value in MHz for -32 grade]
Pin-to-Pin Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns for -32 grade]
Supply Voltage (VCC) — 5 V
Logic Family — Low-power CMOS (LC suffix)
Programming Method — UV-erasable or one-time programmable (OTP for LC windowless variant)
Operating Temperature Range — [DATA_NEEDED: commercial or industrial grade]
I/O Standard — TTL-compatible
MSL Level — unknown

Datasheets & Resources

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