EP910LC-30Y vs EP910JC-30 Comparison
Detailed side-by-side comparison of EP910LC-30Y by Altera and EP910JC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30Y | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.40 | $9.75 |
| Family | Altera Classic EPLD | Classic EPLD (MAX-style) |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | β |
| Supply Voltage | 5 V (TTL-compatible) | β |
| Process Technology | CMOS, UV-erasable / OTP | β |
| Package | PLCC-44 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Operating Temperature | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Speed/Power Grade | LC (low-power, 30ns) | β |
| Processing Flow | Y (extended reliability) | β |
| Logic Compatibility | 100% TTL emulation | β |
| Mounting Type | Surface Mount (PLCC socket) | Surface Mount (socket-mountable) |
| RoHS Status | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS compliance] |
| Propagation Delay (tpd) | β | 30 ns |
| Maximum Internal Frequency (Fmax) | β | 33.3 MHz |
| Inputs | β | 36 |
| Product Terms | β | 240 |
| Outputs | β | 10 dedicated |
| Supply Voltage (Vcc) | β | 5 V |
| Technology | β | CMOS EPROM, UV-erasable |
| Supply Current (Icc) | β | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | β | 24 macrocells (AND/OR array architecture) |