EP910LC-30Y vs EP910JC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-30Y sa pamamagitan ng Altera at EP910JC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-30Y | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (MAX-style) |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| Volte ng Pagbibigay | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Packhaging | PLCC-44 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Temperature na Operasyon | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket) | Surface Mount (socket-mountable) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS compliance] |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EPROM, UV-erasable |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |