EP910LC-30Y vs EP910JC-30 Comparación
Comparación detallada lado a lado de EP910LC-30Y por Altera y EP910JC-30 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-30Y | EP910JC-30 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,40 | $9,75 |
| Family | Altera Classic EPLD | Classic EPLD (MAX-style) |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| Tensión de alimentación | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Encapsulado | PLCC-44 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Temperatura de funcionamiento | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| Tipo de montaje | Surface Mount (PLCC socket) | Surface Mount (socket-mountable) |
| Estado RoHS | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS compliance] |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EPROM, UV-erasable |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |