EP910LC-30Y vs EP910JC-35 Comparison
Detailed side-by-side comparison of EP910LC-30Y by Altera and EP910JC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30Y | EP910JC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.40 | $9.95 |
| Family | Altera Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | β |
| Supply Voltage | 5 V (TTL-compatible) | β |
| Process Technology | CMOS, UV-erasable / OTP | β |
| Package | PLCC-44 | β |
| Operating Temperature | Commercial 0C to +70C | 0C to 70C (Commercial) |
| Speed/Power Grade | LC (low-power, 30ns) | β |
| Processing Flow | Y (extended reliability) | β |
| Logic Compatibility | 100% TTL emulation | β |
| Mounting Type | Surface Mount (PLCC socket) | Surface Mount (PLCC socket recommended) |
| RoHS Status | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: rohs status] |
| Logic Family | β | Classic EPLD (CMOS EPROM) |
| Inputs | β | 36 |
| I/O Pins | β | 24 |
| Propagation Delay (max) | β | 38 ns (tPD) |
| Maximum Clock Frequency | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Package Type | β | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | β | J BEND |
| Package Code | β | QCCJ |
| Package Shape | β | SQUARE |
| Technology | β | CMOS EPROM, UV-erasable / OTP |
| Temperature Grading | β | COMMERCIAL |
| Equivalent Gates | β | Approx. 900 usable gates |