EP910LC-30Y vs EP910JC-35 对比
详细并排对比 EP910LC-30Y 出自 Altera 和 EP910JC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910LC-30Y | EP910JC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $25.40 | $9.95 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| 电源电压 | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封装 | PLCC-44 | — |
| 工作温度 | Commercial 0C to +70C | 0C to 70C (Commercial) |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| 安装类型 | Surface Mount (PLCC socket) | Surface Mount (PLCC socket recommended) |
| RoHS 状态 | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: rohs status] |
| Logic Family | — | Classic EPLD (CMOS EPROM) |
| Inputs | — | 36 |
| I/O Pins | — | 24 |
| Propagation Delay (max) | — | 38 ns (tPD) |
| 最大时钟频率 | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | — | J BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Technology | — | CMOS EPROM, UV-erasable / OTP |
| Temperature Grading | — | COMMERCIAL |
| Equivalent Gates | — | Approx. 900 usable gates |