EP910LC-30Y vs EP910LC30T Comparison
Detailed side-by-side comparison of EP910LC-30Y by Altera and EP910LC30T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30Y | EP910LC30T |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Last Time Buy |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| Supply Voltage | 5 V (TTL-compatible) | 5 V |
| Process Technology | CMOS, UV-erasable / OTP | CMOS (LC low-power variant) |
| Package | PLCC-44 | 44-pin PLCC (J-Lead), Tape and Reel |
| Operating Temperature | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| Mounting Type | Surface Mount (PLCC socket) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS status] |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 450 equivalent gates |
| Propagation Delay | — | 30 ns (tpd) |
| Maximum Frequency | — | 33.3 MHz |
| Programmable Elements | — | UV-erasable EPROM |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Programming Interface | — | Altera ByteBlaster-compatible |
| Manufacturer | — | Intel (formerly Altera); currently supplied by Rochester Electronics |