EP910LC-30Y vs EP910LC30T 比較
詳細並排比較 EP910LC-30Y 由 Altera 與 EP910LC30T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-30Y | EP910LC30T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| 供應電壓 | 5 V (TTL-compatible) | 5 V |
| Process Technology | CMOS, UV-erasable / OTP | CMOS (LC low-power variant) |
| 封裝 | PLCC-44 | 44-pin PLCC (J-Lead), Tape and Reel |
| 工作溫度 | Commercial 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| 安裝類型 | Surface Mount (PLCC socket) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS status] |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 450 equivalent gates |
| Propagation Delay | — | 30 ns (tpd) |
| Maximum Frequency | — | 33.3 MHz |
| Programmable Elements | — | UV-erasable EPROM |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| Programming Interface | — | Altera ByteBlaster-compatible |
| Manufacturer | — | Intel (formerly Altera); currently supplied by Rochester Electronics |