EP910LC-35 vs EP910LC-30 Comparison
Detailed side-by-side comparison of EP910LC-35 by Altera and EP910LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35 | EP910LC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.75 | $22.50 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Classic (EP910) | β |
| Macrocells | 24 | β |
| Usable Gates | 450 | β |
| Propagation Delay (tPD) | 35 ns | 30 ns (max) |
| Maximum Toggle Frequency | 28.6 MHz | 62 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (nominal, TTL) |
| Technology | CMOS EPROM | β |
| Package | PLCC-44 (J-lead, LC suffix) | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Pin Count | 44 | β |
| Programmable Flip-Flops | Yes (per macrocell) | β |
| Output Enable Control | Per macrocell | β |
| Erasure Method | UV (windowed) or OTP (plastic) | β |
| RoHS Status | Not applicable (legacy product) | [DATA_NEEDED: RoHS status] |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | β | 24 |
| Process Technology | β | CMOS (EPROM-based) |
| Package Type | β | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | β | Commercial (0C to +70C) |
| I/O Pin Count | β | 24 |
| Dedicated Input Pins | β | 36 (including I/O) |
| Product Terms per Macrocell | β | Up to 16 |
| Programming Technology | β | UV-erasable EPROM cell |
| Development Tool | β | Altera MAX+PLUS II |
| MSL Level | β | [DATA_NEEDED: MSL level] |