EP910LC-35H vs EP910LC-35 Comparison
Detailed side-by-side comparison of EP910LC-35H by Altera and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35H | EP910LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.00 | $18.75 |
| Family | Classic EPLD (EP910) | Classic (EP910) |
| Logic Elements | 24 macrocells | β |
| Equivalent Gates | 450 usable gates | β |
| Propagation Delay (tpd) | 35 ns | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Package | 40-pin Ceramic DIP (H suffix) | PLCC-44 (J-lead, LC suffix) |
| User I/O Pins | 36 | β |
| Dedicated Inputs | 10 | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | UV (windowed) or OTP (plastic) |
| Programming Method | Altera hardware programmer | β |
| Logic Levels | TTL compatible | β |
| Quiescent Current | [DATA_NEEDED: typical ICC value] | β |
| Process Node | [DATA_NEEDED: process geometry] | β |
| Mounting Type | Through-hole (Ceramic DIP) | β |
| RoHS Status | unknown | Not applicable (legacy product) |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 24 |
| Usable Gates | β | 450 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Toggle Frequency | β | 28.6 MHz |
| Pin Count | β | 44 |
| Programmable Flip-Flops | β | Yes (per macrocell) |
| Output Enable Control | β | Per macrocell |