EP910LC-35H vs EP910LC-35 比較
詳細並排比較 EP910LC-35H 由 Altera 與 EP910LC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-35H | EP910LC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910) | Classic (EP910) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| 封裝 | 40-pin Ceramic DIP (H suffix) | PLCC-44 (J-lead, LC suffix) |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | UV (windowed) or OTP (plastic) |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| 靜態電流 | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| 安裝類型 | Through-hole (Ceramic DIP) | — |
| RoHS 狀態 | unknown | Not applicable (legacy product) |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| 腳位數 | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |