EP910LC-35H vs EP910LC-35 Comparación
Comparación detallada lado a lado de EP910LC-35H por Altera y EP910LC-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-35H | EP910LC-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,00 | $18,75 |
| Family | Classic EPLD (EP910) | Classic (EP910) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Encapsulado | 40-pin Ceramic DIP (H suffix) | PLCC-44 (J-lead, LC suffix) |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | UV (windowed) or OTP (plastic) |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| Corriente en reposo | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| Tipo de montaje | Through-hole (Ceramic DIP) | — |
| Estado RoHS | unknown | Not applicable (legacy product) |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Recuento de pines | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |