EP910LC-40 vs EP910JC-30 Comparison
Detailed side-by-side comparison of EP910LC-40 by Rochester Electronics and EP910JC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 ObsoleteSpecification Comparison
| Parameter | EP910LC-40 | EP910JC-30 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $52.00 | $9.75 |
| Manufacturer | Rochester Electronics (Altera original) | β |
| Device Family | Altera Classic EPLD - EP910 | β |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Usable Gates | 450 | β |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 2 (12 macrocells each) | β |
| Propagation Delay (tPD) | 40 ns | β |
| Maximum Toggle Frequency (fMAX) | 25 MHz | β |
| User I/O Pins | 36 | β |
| Dedicated Inputs | 4 | β |
| Supply Voltage (VCC) | 5 V (single supply) | β |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Package | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Operating Temperature (Commercial) | 0 C to +70 C | β |
| Programming Method | Altera Logic Programmer (PLAD-J), 4-wire serial | β |
| RoHS Status | Not applicable (legacy) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free Status | Not applicable | β |
| Family | β | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | β | 30 ns |
| Maximum Internal Frequency (Fmax) | β | 33.3 MHz |
| Inputs | β | 36 |
| Product Terms | β | 240 |
| Outputs | β | 10 dedicated |
| Supply Voltage (Vcc) | β | 5 V |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Supply Current (Icc) | β | [DATA_NEEDED: Icc typical / maximum] |
| Mounting Type | β | Surface Mount (socket-mountable) |
| Logic Blocks | β | 24 macrocells (AND/OR array architecture) |