EP910LC-40 vs EP910JC-30 Vergleich
Detaillierter Direktvergleich von EP910LC-40 von Rochester Electronics und EP910JC-30 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 ObsoleteSpezifikationsvergleich
| Parameter | EP910LC-40 | EP910JC-30 |
|---|---|---|
| Marke | Rochester Electronics | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $52,00 | $9,75 |
| Manufacturer | Rochester Electronics (Altera original) | — |
| Device Family | Altera Classic EPLD - EP910 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 450 | — |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 2 (12 macrocells each) | — |
| Propagation Delay (tPD) | 40 ns | — |
| Maximum Toggle Frequency (fMAX) | 25 MHz | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Gehäuse | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Operating Temperature (Commercial) | 0 C to +70 C | — |
| Programming Method | Altera Logic Programmer (PLAD-J), 4-wire serial | — |
| RoHS-Status | Not applicable (legacy) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free Status | Not applicable | — |
| Family | — | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Montageart | — | Surface Mount (socket-mountable) |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |