EP910LI-30T vs EP910LI-35BF Comparison
Detailed side-by-side comparison of EP910LI-30T by Altera and EP910LI-35BF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-30T | EP910LI-35BF |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Clock-to-Output (tCO) | [DATA_NEEDED: tCO] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| Package | PQCC-44 (J-lead) | 44-pin PLCC (J-lead) |
| Operating Temperature | -40C to +85C (Industrial) | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| Supply Voltage | [DATA_NEEDED: VCC] | — |
| Mounting Type | Surface Mount | — |
| Programming Method | EPROM (UV-erasable) via Altera Logic Programmer | EPROM/UV-erase programmer (Altera Classic algorithm) |
| RoHS Status | [DATA_NEEDED: RoHS] | — |
| Lead-Free | [DATA_NEEDED: Lead-free] | — |
| Device Family | — | Altera Classic EPLD |
| Part Number Base | — | EP910 |
| Logic Density | — | 450 usable gates |
| Macrocells | — | 24 |
| Maximum Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Operating Temperature Range | — | Industrial (LI suffix) |
| Output Polarity Control | — | Programmable XOR per macrocell |
| Flip-Flop Type | — | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | — | 100% TTL emulation |
| Compliance / EOL Status | — | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |