EP910LI-30T vs EP910LI-35BF 比較
詳細並排比較 EP910LI-30T 由 Altera 與 EP910LI-35BF 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-30T | EP910LI-35BF |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Clock-to-Output (tCO) | [DATA_NEEDED: tCO] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| 封裝 | PQCC-44 (J-lead) | 44-pin PLCC (J-lead) |
| 工作溫度 | -40C to +85C (Industrial) | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| 供應電壓 | [DATA_NEEDED: VCC] | — |
| 安裝類型 | Surface Mount | — |
| Programming Method | EPROM (UV-erasable) via Altera Logic Programmer | EPROM/UV-erase programmer (Altera Classic algorithm) |
| RoHS 狀態 | [DATA_NEEDED: RoHS] | — |
| Lead-Free | [DATA_NEEDED: Lead-free] | — |
| Device Family | — | Altera Classic EPLD |
| Part Number Base | — | EP910 |
| Logic Density | — | 450 usable gates |
| Macrocells | — | 24 |
| Maximum Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| 工作溫度範圍 | — | Industrial (LI suffix) |
| Output Polarity Control | — | Programmable XOR per macrocell |
| Flip-Flop Type | — | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | — | 100% TTL emulation |
| Compliance / EOL Status | — | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |