EP910LI-30T vs EP910LI-35BF Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-30T sa pamamagitan ng Altera at EP910LI-35BF sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-30T | EP910LI-35BF |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Clock-to-Output (tCO) | [DATA_NEEDED: tCO] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| Packhaging | PQCC-44 (J-lead) | 44-pin PLCC (J-lead) |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC] | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Programming Method | EPROM (UV-erasable) via Altera Logic Programmer | EPROM/UV-erase programmer (Altera Classic algorithm) |
| Tindminan RoHS | [DATA_NEEDED: RoHS] | — |
| Lead-Free | [DATA_NEEDED: Lead-free] | — |
| Device Family | — | Altera Classic EPLD |
| Part Number Base | — | EP910 |
| Logic Density | — | 450 usable gates |
| Macrocells | — | 24 |
| Maximum Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Hanay ng Temperature na Operasyon | — | Industrial (LI suffix) |
| Output Polarity Control | — | Programmable XOR per macrocell |
| Flip-Flop Type | — | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | — | 100% TTL emulation |
| Compliance / EOL Status | — | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |